| Paketname | verilator |
| Beschreibung | fast free Verilog simulator |
| Archiv/Repository | Offizielles Debian Archiv squeeze (main) |
| Version | 3.803-1 |
| Sektion | electronics |
| Priorität | optional |
| Installierte Größe | 7024 Byte |
| Hängt ab von | libc6 (>= 2.1.3), libgcc1 (>= 1:4.1.1), libstdc++6 (>= 4.4.0) |
| Empfohlene Pakete | |
| Paketbetreuer | Debian Electronics Team |
| Quelle | |
| Paketgröße | 2662532 Byte |
| Prüfsumme MD5 | 1fa49c7d3890a300b3cc19c38b4eb3e5 |
| Prüfsumme SHA1 | df5efcfa62b0d48a0e1def2092bd9050246d1818 |
| Prüfsumme SHA256 | 5ffb9774f43ca5f8c7898f1d1410fd06bbb714cea6d06b6528500976c6e98873 |
| Link zum Herunterladen | verilator_3.803-1_i386.deb |
| Ausführliche Beschreibung | Verilator is the fastest free Verilog HDL simulator, and beats many commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus
some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
It is designed for large projects where fast simulation performance is of
primary concern, and is especially well suited to generate executable models
of CPUs for embedded software design teams.
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